With the increasing complexity of large-scale integrated circuit chips, the number of input and output connections that have to be made to a chip has correspondingly increased. This trend has encouraged the evolution from dual in-line chip packages, which have two parallel rows of connection pins, to smaller and denser leadless chip carriers. Leadless chip carriers generally consist of a package containing a square plate of ceramic, such as alumina, which forms a chip carrier or base onto which a chip is mounted. The chip carrier is then surface mounted, usually onto a generally larger printed circuit board or other ceramic chip carriers, simply by placing the carrier on top of corresponding contact pads which mirror those contact pads of the chip carrier.
An electrical and mechanical connection is then made by soldering the chip carrier to this generally larger board by reflow soldering. Electrical connection paths within the leadless chip carrier allow the pads of the chip to be brought to external contact pads formed around each of the four sides of the ceramic base of the carrier. One technique for providing the electrical connection path comprises wire bonding of the leads of the chip to the external contacts. During this process very thin wires may be manually or automatically placed between the die pads and the bond fingers of the package to provide the electrical connections. This arrangement is less cumbersome than mounting dual in-line packages onto a board and allows greater density of input and output connections to be achieved.
In order to eliminate the expense, and complexity of wire bonding process, a so-called flip-chip technology was initiated. In this technology a bumped chip or die which carries a pad arrangement on a major top surface is turned upside-down, i.e. flipped, allowing direct coupling between the pads and matching contacts on the main circuit board or the chip carrier. The direct connection is facilitated by growing solder or gold bumps formed on the chip's input/output terminals. The flipped bumped chip is otherwise referred to as a flip-chip. The flip-chip is then aligned to the chip carrier and all connections are made simultaneously by reflowing the solder.
As schematically illustrated in FIG. 1, a flip-chip package 10 comprises a die 12 mounted on a die carrier or package 14. The die 12 includes an array of bumps 16 which are bonded to the package 14. Pins 18 corresponding to the bumps 16 are provided on the package 14 for connecting the flip-chip package 10 to a printed circuit board (PCB) 20.
One of the first steps in the flip-chip package design is routing the bumps 16 to the package pins 18. Traditional drafting packages commonly used for traditional IC package design have proven inadequate for advanced IC package design, such as flip-chip package design. Designer productivity and the quality of the final results are limited due to the lack of specialized capabilities in the tool, such as the ability to treat the chip and the chip carrier as a single open area as required for flip-chip package design.
Traditional PCB layout tools and software based on them are likewise limited in their usefulness for advanced IC package design. For example, because PCB layout tools focus on managing complex logical interconnects among large number of nets and components, they typically draw data from netlists. By contrast, the logic of a single-chip package is relatively simple--designers focus on connecting the chip bump to the most convenient package pin for maximum density.
While drafting packages and modified PCB layout tools can be used to design flip-chip packages in low volumes, the design process is slow and the results rarely optimized for production. Therefore, when manufacturing companies begin to adopt advanced IC packaging in higher volumes, routing tools developed specifically for the unique challenges of IC package design become necessary to achieve higher throughput and manufacturing yields.
Accordingly, it would be desirable to create a single-layer autorouter for routing interconnects in advanced IC packages such as flip-chip packages.